1. Field of the Invention
The invention relates to a process for Low Temperature Oxide (LTO) deposition of a backside seal for wafers using Low Pressure Plasma Enhanced Chemical Vapour Deposition (LPPECVD) and in particular to a two layer LTO backside seal.
2. Background Art
Autodoping is a problem that occurs in silicon wafers that are used for epitaxial deposition. During the heat cycle of the epitaxial process, the highly doped (p+) silicon substrates diffuse out dopant atoms through the backside of the substrate leading to an unintentional overdoping effect on the wafer frontside. This is most noticeable at the edge of the wafer. This leads to an inhomogeneity in the epitaxial dopant profile beyond the tolerance of most device manufacturers.
A backside layer on the wafer reduces the autodoping effect.
Various technologies are used for the deposition of a SiO2 layer. These can roughly be divided into atmospheric and low-pressure applications and further into processes that utilize the ignition of plasma (plasma enhanced: PE) in chemical vapour deposition (CVD), which makes used of pyrolytic surface-catalysis of silicon and oxygen bearing carrier gases.
Haze or epi-haze is non-localised light scattering resulting from uneven surface topography (micro-roughness) or from dense concentrations of surface or near surface imperfections. Semiconductor wafers should have low or no epi-haze.
Film stress is the compressive or tensile forces that affect the film on a wafer. A wafer layer with high film stress is more vulnerable to warpage than a wafer layer with low film stress.
One existing system provides a single LTO layer on the backside of a wafer. However the layer produced is typically thicker than 500 nm and does not solve the problems of haze on the front face of the wafer and warpage of the wafer.